000			03364 a2200337 4500
005			20260313171917.0
020			_a9781119778097 _q(ebook)
020			_a9781119778066 _q(pdf)
020			_a9781119778080 _q(epub)
020			_z9781119778042 _q(hardback)
050	0	0	_aTK7874.75
082	0	0	_aE 621.395028553 T835 2022 _223
100	1		_aTripathi, Suman Lata, _eauthor.
245	1	0	_aDigital VLSI design and simulation with Verilog / _cSuman Lata Tripathi, Sobhit Saxena, Sanjeet Kumar Sinha, Govind Singh Patel.
264		1	_aHoboken, NJ : _bJohn Wiley & Sons, _c2022.
300			_a1 online resource
504			_aIncludes bibliographical references and index.
520			_a"The integrated circuits are now growing its importance in every electronic system that needs an efficient VLSI architecture designs with low power consumption, compress chip area, speed, and operating frequency. The challenge for VLSI system designers is to optimize the hardware-software integration for lowering the total cost of acquisition of products. So, there is a demand for better technological solutions for advanced VLSI architectures that can be done through hardware description language (HDL). Verilog HDL is one of the programming languages that can give better solutions to this new era of the VLSI industry. The prefabrication design and analysis of such advanced VLSI architecture can be easily implemented with Verilog HDL with the available software tools like Xilinx and Cadence. The presented book mainly deals with fundamental concepts of digital design along with their design verification with Verilog HDL. The book will be a common source of knowledge for the beginners as well as research seeking students working in the area of VLSI design covering fundamentals of digital design from switch level to FPGA based implementation using hardware description language (HDL). The book is summarized in 10 chapters. Chapter 1 and 2 describes the fundamental concepts behind digital circuit design including combinational and sequential circuit design. Chapter 3 to chapter 8 is focused on sequential and combinational circuit design using Verilog HDL at a different level of abstractions in Verilog coding. Chapter 9 includes implementation of any logic function using a programmable logic device like PLD, CPLD or FPGA, etc. Chapter 10 covers a few real-time examples of digital circuit design using Verilog. Chapter 11 focuses on System Verilog, distinct features, computing Verilog and System Verilog with design example."-- _cProvided by publisher.
526			_aE
588			_aDescription based on print version record and CIP data provided by publisher; resource not viewed.
650		0	_aIntegrated circuits _xVery large scale integration _xDesign and construction.
650		0	_aVerilog (Computer hardware description language)
700	1		_aSaxena, Sobhit, _eauthor.
700	1		_aSinha, Sanjeet Kumar, _eauthor.
700	1		_aPatel, Govind Singh, _eauthor.
776	0	8	_iPrint version: _aTripathi, Suman Lata. _tDigital VLSI design and simulation with Verilog _dHoboken, NJ : John Wiley & Sons, 2022 _z9781119778042 _w(DLC) 2021020790
856			_uhttps://drive.google.com/file/d/12zNkyZsH4CvdU-0F_VggW-c8E8j150sq/view?usp=sharing
906			_a7 _bcbc _corignew _d1 _eecip _f20 _gy-gencatlg
942			_2ddc _cEB
999			_c40701 _d40701